1. Field of the Invention
The present invention relates to a flash A/D (analog-digital) converter for converting an analog signal into digital signal.
2. Description of the Related Art
A flash A/D converter, which is one of the parallel A/D converters, has been widely used. The flash A/D converter divides a predetermined voltage through a plurality of voltage-dividing resistances connected in series to generate a plurality of reference voltages, compares the respective reference voltages with an analog input signal voltage at each comparator, and based on a result obtained by the comparison, outputs digital signal corresponding to the analog input signal.
The flash A/D converter is typically configured by the comparators corresponding to a resolution (in a case of an n-bit A/D converter, for example, 2n−1 pieces of comparators) Thus, as the resolution is raised, a circuit size is exponentially increased. Accordingly, power consumption is increased, and a chip size becomes large. In addition, since a large number of comparators (2n−1 pieces of comparators, for example) are connected to the input signal, an input capacitance is increased, and whereby power consumption is increased and a high-speed operation is inhibited as well.
Hence, there is proposed a flash A/D converter which uses an interpolation technology to prevent the increase in circuit size and reduce the input capacitance, and enables a high-speed operation with a low power consumption (see “Description of the Related Art” of Japanese Unexamined Patent Application Publication No. JP 2003-218697, Patent Document 1).
A configuration of the flash A/D converter using the interpolation technology (hereinafter, referred to as an “interpolation flash A/D converter”) is shown in FIG. 7. A flash A/D converter 100 includes a sample-hold (T/H) circuit 111, a reference voltage (referred voltage) generation circuit 112, a first group of amplifiers 113, an interpolation circuit 114, a second group of amplifiers 115, a group of comparators 116, an encoder 117, and a timing generator 118.
The sample-hold circuit 111 samples voltage of an analog signal to be inputted (hereinafter, referred to as an “analog input signal”), and holds the sampled value for a certain time period. The reference voltage generation circuit 112 is configured by a plurality of voltage-dividing resistances (hereinafter, referred to as “ladder resistances”) connected in series, and generates a plurality of reference voltages having different voltage.
In the first group of amplifiers 113, a difference voltage between each reference voltage generated by the reference voltage generation circuit 112 and the input signal voltage held by the sample-hold circuit 111 is amplified by each of a plurality of amplifiers A101. The second group of amplifiers 115 includes a plurality of amplifiers A103 for amplifying voltage in which a portion between output voltages of the amplifiers A101 whose levels of an inputted reference voltage are adjacent to each other is interpolated by an interpolation circuit 114, in addition to a plurality of amplifiers A102 each of which amplifies an output voltage of each amplifier in the first group of amplifiers 113. The output voltage of each of the amplifiers A102 and A103 is sequentially compared by each comparator CMP 100 of the group of comparators 116. The encoder 117 encodes based on a result of the comparison, and whereby, the digital signal is obtained. The sample-hold circuit 111 and the encoder 117 operate in synchronization with signals CKTH and CKMCL to be outputted from the timing generator 118.
Thus, in the interpolation flash A/D converter, the number of the amplifiers A101 of the first group of amplifiers 113 is reduced to the half thereof while in the second group of amplifiers 115, interpolation voltages are each generated from the output voltages of the two mutually adjacent amplifiers A101 of the first group of amplifiers 113, in order to obtain a comparator output corresponding to a resolution.
Therefore, the number of preamplifiers of the first group of amplifiers 113 may be reduced to the half thereof and an A/D converter capable of performing a high-speed operation with a low electric power consumption may be provided.